Title: Attribute Evaluation On A Shared-Memory Multiprocessor (thesis defense)
Modern computer processors are often equipped with two, three, four or even more cores.
For a computer program to take advantage of these extra computing units, often large modifications
are required. In my thesis defense I will present a method and an implementation that can generate
parallel AG evaluators in addition to sequential evaluators. The implementation is an extension to the
UUAG compiler. It allows your existing AG to benefit from those extra horsepowers
involving a minimal amount of modifications. Furthermore I will explain the problems that may arise
when taking my approach.